Digital design / Verification
I designed and implemented a codeword detector on a Basys 3 FPGA using a 24-bit linear-feedback shift register, a Moore finite state machine and a counter. The system detects overlapping occurrences of the six-bit sequence 011000 in a pseudorandom bitstream, then presents the results on the board's LEDs and seven-segment display.
01 / Implementation
The hardware demonstration runs at 5 Hz so the changing bit sequence is visible. LEDs show the pseudorandom output and the end-of-sequence signal, while the seven-segment display shows the detection count. A switch selects between groups of counter digits, and the centre button resets the system.
The design connects the clock divider, sequence generator, detector, counter and display multiplexer through a top module. This separates the detection logic from the board interface and makes the individual blocks easier to verify.
02 / System design
The 24-bit maximum-length LFSR uses taps at positions 24, 23, 22 and 17. Its output feeds a seven-state Moore machine designed to recognise 011000 while preserving partial matches, allowing overlapping codewords to be detected.
I verified the FSM and counter with controlled 36-bit input sequences, including overlapping matches, a sequence ending with a codeword, reset and end-of-sequence events. The testbench accounts for the extra cycle between a Moore state transition and the counter response.
Short top-level simulations checked signal timing, followed by a complete run of the 2^24 - 1 sequence. The simulation recorded 262,144 detections, matching the expected count. The report also identifies broader input-sequence coverage as a useful next step.